1. Field of the Invention
The present disclosure relates to manufacturing methods for semiconductor memory devices and, more particularly, to fabrication methods and structures for providing recessed channels in nonvolatile memory devices.
This U.S. non-provisional patent application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 2005-103866 filed on Nov. 1, 2005, and Korean Patent Application No. 2006-55061 filed on Jun. 19, 2006, the entire contents of which are hereby incorporated by reference.
2. Description of Related Art
With higher integration of semiconductor devices, various physical limitations may affect the performance of the semiconductor devices. For example, because of high integration densities, a channel length of the device may become shorter. The shorter channel length of the device may lead to problems such as, for example, a punch-through effect. In order to overcome such limitations associated with the channel length of the semiconductor device, various structures and fabrication methods for extending a channel length in a highly integrated semiconductor device have been studied.
One such example of a highly integrated semiconductor device includes a recessed channel array transistor (RCAT). The structure of the RCAT includes sidewalls and a recessed region. Specifically, the bottom of the recessed region is used for a channel region.
A conventional method for fabricating a nonvolatile memory device having the recessed channels is as follows. A device isolation layer is formed in a semiconductor substrate. This device isolation layer may be used to define an active region. Furthermore, the defined active region may include the channel for the semiconductor device. Specifically, the recessed region for the channel is formed in the active region. In addition, the recessed region may have a width smaller than that of the active region. Thus, it may be beneficial to form a photoresist pattern having an opening that is smaller than the dimensions of the active region. In particular, the opening of the photoresist pattern defines the recessed region.
While the disclosed RCAT provides for higher integration densities in semiconductor devices, it suffers from several shortcomings. For example, with higher integration of semiconductor devices, it may become more difficult to precisely arrange the photoresist pattern having a smaller opening.
In addition, the higher integration of nonvolatile semiconductor devices also leads to narrower widths of floating gates. The narrow widths of floating gates may also cause many problems. For example, the narrow floating gates may have insufficient processing margins because of the gates' reduced width. This reduction in processing margins may make it difficult to compensate for the misalignment that occurs when patterning the floating gates. In order to solve this problem, the floating gates may be arranged in self-alignment with the device isolation layer. In this case, the device isolation layer is designed to have a height corresponding to a height of the floating gates. However, it may be practically very difficult to implement such a precise photoresist pattern for the recessed regions in the structure of the device isolation layer having a high surface. This is because the depth of focus (DOF) margin becomes smaller because of such a physical limitation.
The present disclosure is directed towards overcoming one or more problems associated with the prior art semiconductor devices.